Marcin Lukowiak Headshot

Marcin Lukowiak

Professor

Department of Computer Engineering
Kate Gleason College of Engineering
mxleec@rit.edu
585-475-2808
Office Location
GLE-3439

Marcin Lukowiak

Professor

Department of Computer Engineering
Kate Gleason College of Engineering

Education

MS, Ph.D., Poznan University of Technology (Poland)

Bio

Dr. Lukowiak earned his dual B.S. and M.S. degrees in Control and Systems Engineering, and his Ph.D. in Electrical Engineering from Poznan University of Technology. His current research interests are concentrated in the applied cross-disciplinary area related to reconfigurable computing, hardware and hardware-software systems, cryptographic engineering, and high performance computing. As a graduate student Dr. Lukowiak worked on applications of switched-current (SI) technique in low power, high-speed circuits for filtering and video processing and development of new methods and tools for automated synthesis of low sensitive SI circuits. For more about Dr. Lukowiak, see his personal website. 

Select Publications:

· M. Lukowiak, A. Meneely, S. Radziszowski, J. Vallino, and C. Wood, “Developing an Applied,

o Security-Oriented Computing Curriculum,” Proceedings of the ASEE 2012, San Antonio, Texas, June 2012.

· D. Webster and Marcin Lukowiak. “Versatile FPGA Architecture for Skein Hashing Algorithm,” Proceedings of ReConFig'2011, Cancun, Mexico, November 2011, pp. 268-273.

· F. Hu, Q. Hao, M. Lukowiak, Q. Sun, K. Wilhelm, S. Radziszowski, and Y. Wu, “Trustworthy Data Collection from Implantable Medical Devices via High-Speed Security Implementation Based on IEEE 1363,” IEEE Transactions on Information Technology in Biomedicine, 14(6), 2010, pp. 1397-1404.

· A. Fitzgerald, M. Lukowiak, M. Kurdziel, C. Mackey, K. Smith Jr, B. Boorman, D. Harris, and W. Skiba, “FPGA-Based, Multi-Processor HW-SW System for Single-Chip Crypto Applications,” Proceedings of MILCOM'2010, San Jose, CA, USA, November 2010, pp. 1317-1322.

· J. Espenshade, M. Lukowiak, M. Shaaban, and G. von Laszewski, “Flexible Framework for Commodity FPGA Cluster Computing,” Proceedings of FPT’2009, December 2009, Sydney, Australia, pp. 465-471.

· X. Tran, M. Lukowiak, and S. Radziszowski, Effectiveness of Variable Bit-Length Power Analysis Attacks on SHA-3 Based MAC, in Proceedings of MILCOM'2016, Baltimore, MD, November 2016.

· J. Lowden, M. Lukowiak, S. Lopez-Alarcon, Design and performance analysis of efficient Keccak tree hashing on GPU architectures, Journal of Computer Security 23(5): 541-562, 2015.

· M. Lukowiak, S. Radziszowski, J. Vallino, and C. Wood, Cybersecurity Education: Bridging the Gap between Hardware and Software Domains, ACM Transactions on Computing Education, 14(1), 2014.

· S. Skalicky, S. Lopez, and M. Lukowiak, Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs, Computers and Electrical Engineering, 40(4), 2014.

· M. Kurdziel, M. Lukowiak, and M. Sanfilippo, Minimizing Performance Overhead in Memory Encryption, Journal of Cryptographic Engineering, Volume 3, Issue 2, Springer 2013.

mxleec@rit.edu
585-475-2808

Select Scholarship

Published Conference Proceedings
Werner, Gordon, et al. "Implementing Authenticated Encryption Algorithm MK-3 on FPGA." Proceedings of the MILCOM. Ed. MILCOM. Baltimore, MD: IEEE, Web.
Tran, Xuan, Marcin Lukowiak, and Stanislaw Radziszowski. "Effectiveness of Variable Bit-Length Power Analysis Attacks on SHA-3 Based MAC." Proceedings of the MILCOM. Ed. MILCOM. Baltimore, MD: IEEE, Web.
Skalicky, Samuel, et al. "Designing Customized ISA Processors using High Level Synthesis." Proceedings of the ReConFig. Ed. ReConFig. Cancun, Mexico: IEEE, Web.
Kelly, Matthew, et al. "Customizable Sponge-Based Authenticated Encryption Using 16-bit S-boxes." Proceedings of the MILCOM. Ed. MILCOM. Tampa, FL: IEEE, Web.
Wood, Christopher, Stanislaw Radziszowski, and Marcin Lukowiak. "Affine-Power S-Boxes over Galois Fields with Area-Optimized Logic Implementations." Proceedings of the MILCOM. Ed. MILCOM. Tampa, FL: IEEE, Web.
Skalicky, Samuel, et al. "A Parallelizing Matlab Compiler Framework and Run Time for Heterogeneous Systems." Proceedings of the HPCC-CSS-ICESS. Ed. Lisa O'Conner. New York, NY: IEEE, Web.
Skalicky, Sam, Sonia Lopez, and Marcin Lukowiak. "Mission Control: A Performance Metric and Analysis of Control Logic for Pipelined Architectures on FPGAs." Proceedings of the ReConFig'2014, 8-10 December 2014, Cancun, Mexico. Ed. Michael Huebner, Mike Wirthlin, and Rene Cumplido. Cancun, Mexico: IEEE Xplore, Web.
Skalicky, Sam, Sonia Lopez, and Marcin Lukowiak. "Enabling FPGA support in MATLAB based Heterogeneous Systems." Proceedings of the ReConFig'2014, 8-10 December 2014, Cancun, Mexico. Ed. Michael Huebner, Mike Wirthlin, and Rene Cumplido. Cancun, Mexico: IEEE Xplore, Web.
Skalicky, S., S. Lopez, and M. Lukowiak. "Distributed Execution of Transmural Electrophysiological Imaging with CPU, GPU, and FPGA." Proceedings of the International Conference on ReConFigurable Computing and FPGAs. Ed. E. de la Torre, M. Wirthlin, and R. Cumplido. Cancun, Mexico: IEEE, Print.
Skalicky, S., et al. "High Level Synthesis: Where Are We? A Case Study on Matrix Multiplication." Proceedings of the International Conference on ReConFigurable Computing and FPGAs. Ed. E. de la Torre, M. Wirthlin, and R. Cumplido. Cancun, Mexico: IEEE, Print.
Skalicky, S., et al. "Linear Algebra Computations in Heterogeneous Systems." Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors. Ed. E. El-Araby. Ashburn, VA: IEEE, Print.
Skalicky, S., et al. "Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs." Proceedings of the International Symposium on Applied Reconfigurable Computing. Ed. P. Brisk, J. de Figueiredo Coutinho, and P. Diniz. Los Angeles, CA: Springer, Print.
Webster, David and Marcin Lukowiak. "Versatile FPGA Architecture for Skein Hashing Algorithm." Proceedings of the 2011 International Conference on ReConFigurable Computing and FPGAs. Ed. Peter Athanas, Juergen Becker, and Rene Cumplido. Cancun, Mexico: IEEE Xplore, Computer Society CPS, 2011. Web.
Bobrov, Max, et al. "Effects of GPU and CPU Loads on Performance of CUDA Applications." Proceedings of the 2011 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'11. Ed. Hamid R. Arabnia. Las Vegas, NV: CSREA Press, 2011. Print.
Shows/Exhibits/Installations
Lukowiak, Marcin. Efficient hardware implementations of MK-3. By Alan Kaminsky, et al. 7 Apr. 2016. CEIS University Technology Showcase 2016, Rochester. Exhibit.
Journal Paper
Lowden, Jason, Marcin Lukowiak, and Sonia Lopez-Alarcon. "Design and Performance Analysis of Efficient Keccak Tree hashing on GPU Architectures." Journal of Computer Security 23. 5 (2015): 541-562. Print.
Lukowiak, Marcin, et al. "Cybersecurity Education: Bridging the Gap Between Hardware and Software Domains." ACM Transactions on Computing Education (TOCE) 14. 1 (2014): 2:1-2:20. Web.
Bajorski, Peter, et al. "Stochastic Analysis and Modeling of a Tree-Based Group Key Distribution Method in Tactical Wireless Networks." Journal of Telecommunications System & Management 3. 2 (2014): 1-8. Web.
Skalicky, Sam, Sonia Lopez, and Marcin Lukowiak. "Performance Modeling of Pipelined Linear Algebra Architectures on FPGAsPerformance Modeling of Pipelined Linear Algebra Architectures on FPGAs." Computers & Electrical Engineering 40. 4 (2014): 1015-1027. Web.
Kurdziel, M., M. Lukowiak, and M. Sanfilippo. "Minimizing Performance Overhead in Memory Encryption." Journal of Cryptographic Engineering 3. 2 (2013): 129-138. Print.
Provisional Patent
Bajorski, Peter, et al. "Electronic Key Management Using PKI to Support Group Key Establishment in the Tactical Environment." Patent 8,873,759. 28 Oct. 2014.
Book Chapter
Hu, F., et al. "Implantable Medical Device Security From a Machine Learning Perspective." Telehealthcare Computing and Engineering: Principles and Design. Ed. F. Hu. Boca Raton, FL: CRC Press, 2013. 699-708. Print.
Invited Keynote/Presentation
Lukowiak, Marcin. "Multi-Disciplinary Applied Cryptography." 2011 CCLI/TUES Principal Investigators (PIs) Conference. The American Association for the Advancement of Science (AAAS) Education and Human Resources Programs (EHR) and the National Science Foundation (NSF) Division of Undergraduate Education (DUE). Washington, D.C., Washington, D.C. 26-28 Jan. 2011. Conference Presentation.
Published Article
Fitzgerald, Andrew, Marcin Lukowiak, Michael Kurdziel,Christopher Mackey, Kenneth Smith Jr, Brian Boorman, Duncan Harris, and WilliamSkiba. “FPGA-based, Multi-processor HW-SW System for Single-Chip Crypto Applications.” IEEE 2010 Military Communications Conference (MILCOM’2010).31 Oct - 3 Nov 2010. 1317-1322. Web. "  É  *
Smith Jr, Kenneth, Marcin Lukowiak. “Methodology for Simulated Power Analysis Attacks on AES.” IEEE 2010 Military CommunicationsConference (MILCOM’2010).31 Oct - 3 Nov 2010. 1292-1297. Web. "  *
Zalewski, Przemyslaw, Lukowiak Marcin, and Radziszowski Stanislaw. “Case Study on FPGA Performance of Parallel Hash Functions.” Electrical Review,(2010): 151-155. Web. "  *
Fei, Hu, Qi Hao, Marcin Lukowiak, Qingquan Sun, Kyle Wilhelm, Stanislaw Radziszowski and Wu Yao. “Trustworthy Data Collection fromImplantable Medical Devices via High-Speed Security Implementation Based on IEEE 1363.” IEEE Transactions on Information Technology in Biomedicine, 14.6 (2010): 1397-1404. Print. " *
Fei, Hu, Xiaojun Cao, Kyle Wilhelm, Marcin Lukowiak and StanislawRadziszowski. “NTRU-based confidential data transmission in telemedicine sensor networks.” Security in Ad Hoc and SensorNetworks, 2010. 159-192. Web. "  -

Currently Teaching

CMPE-160
Digital System Design I
3 Credits
This course covers the specification, analysis, modeling and design of digital systems. Standard modules, such as decoders, multiplexers, shifter registers, adders, and counters, will be analyzed. Lectures will discuss fundamental design methodologies, state machines, and digital system modeling with the use of VHDL as a hardware description language. The laboratory provides hands-on experiences of the design, modeling, implementation, and testing of digital systems using commercial IC components as well as CAD tools.
CMPE-161
Introduction to VHDL
0 Credits
This course presents different approaches to digital system modeling and design with the use of VHDL. The lab sessions include specification and design of combinational and sequential systems. Industry-standard simulation tools will be used in the course, which will enable students gain hands-on experience.
CMPE-260
Digital System Design II
4 Credits
This course presents modern approaches to the design, modeling and testing of digital system. Topics covered are: VHDL and Verilog HDL as hardware description languages (HDLs), simulation techniques, design synthesis, verification methods, and implementation with field programmable gate arrays (FPGAs). Combinational and both the synchronous and asynchronous sequential circuits are studied. Testing and design for testability techniques are emphasized and fault tolerant and fail safe design concepts are introduced. Laboratory projects that enable students gain hands-on experience are required. The projects include complete design flow: design of the system, modeling using HDLs, simulation, synthesis and verification.
CMPE-660
Reconfigurable Computing
3 Credits
The objective of this course is to present the foundations of reconfigurable computing methodologies from both hardware and software perspectives. Topics covered are: architectures of modern field programmable gate arrays (FPGAs), digital system design methodologies using FPGAs, hardware-software co-design with embedded processors, hardware optimization techniques, system level integration under operating system, dynamic reconfiguration. Laboratory projects in which students will acquire a solid capability of Xilinx CAD tools and FPGA devices are required. The projects include the whole design flow: design of the system, VHDL modeling, software and hardware development, FPGA verification.
CMPE-661
Hardware and Software Design for Cryptographic Applications
3 Credits
The objective of this course is to build knowledge and skills necessary for efficient implementations of cryptographic primitives on reconfigurable hardware. The implementation platform will be a field programmable gate array (FPGA) containing a general purpose processor and additional reconfigurable fabric for implementations of custom hardware accelerators. In the studio format, team projects require design of selected cryptographic primitives followed by comparison and contrast of various implementation alternatives, such as software, custom FPGA hardware, and hybrid hardware-software co-design. Project teams are ideally composed of one Computer Engineering student and one Software Engineering or Computer Science student. Computer Engineering students lead the hardware design portions of each project, and Software Engineering and Computer Science students lead the software development portions. Topics may include binary finite field arithmetic, block ciphers, hash functions, counter mode of operation for block ciphers, public key cryptosystems, hardware/software co-design methodologies with FPGAs, software development and profiling, high level synthesis, on-chip buses, hardware/software interfaces, custom hardware accelerators and side channel attacks.

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