Micron chief technologist speaks Wednesday

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Thomas Pawlowski, chief technologist at Micron Technology Inc.

There is no shortage of architecture scaling challenges facing the computing world: logic and memory scaling, bandwidth, throughput and energy proportionality, for example. But according to Thomas Pawlowski, chief technologist at Micron Technology Inc., computer engineers and scientists have a unique opportunity to develop systems that will improve capacity, use and growth of today’s microprocessors.

Pawlowski will discuss new technology directions in computing system architectures at noon on Wednesday, Oct. 29 in the Xerox Auditorium in RIT’s Kate Gleason College of Engineering.

The event is free and open to students, faculty and staff.

A Fellow and chief technologist with Micron’s Architecture Development Group, Pawlowski created or co-created numerous memory architectures and concepts that have become universal to embedded systems and semiconductor technologies including several “firsts”: double data rate memory, 3D memory concepts and the root hardware architecture of Micron’s newly developed, nondeterministic Finite Automata Processor—all central functions of the computer’s ability to transfer data at higher, more efficient rates.

In his talk, he’ll discuss interfaces and new ways of implementing processing using memory rather than logic as the underlying fabrication technology and more about the new Micron Automata Processor, a new computing architecture that leverages DRAM—dynamic random-access memory—addressing problems that until now have been considered unsolvable. He also will discuss the future of processor/memory systems.

Pawlowski earned a Bachelor of Applied Science degree in electrical engineering from the University of Waterloo (Ontario, Canada) and has more than 100 U.S. patents related to memory systems. In his spare time, Pawlowski designs and builds loudspeakers, custom tools and he has completed more than half of the design and fabrication of a revolutionary electric car concept.