Mark Indovina Headshot

Mark Indovina

Senior Lecturer

Department of Electrical and Microelectronic Engineering
Kate Gleason College of Engineering

585-475-6614
Office Hours
Please email me for an appointment.
Office Location
Office Mailing Address
KGCOE Building 9 3rd Floor

Mark Indovina

Senior Lecturer

Department of Electrical and Microelectronic Engineering
Kate Gleason College of Engineering

Education

MS, Rochester Institute of Technology

Bio

Mr. Mark A. Indovina received his AAS, BSEE, and MSEE from
Rochester Institute of Technology. His graduate focus areas
were integrated circuit (IC) design and digital signal processing
(DSP).

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Select Scholarship

Peer Reviewed/Juried Poster Presentation or Conference Paper
Agbalessi, Christie and Mark A. Indovina. "CNNET: A Configurable Hardware Accelerator for Efficient Inference of 8-bit Fixed-Point CNNs." Proceedings of the 2023 IEEE 36th International System-on-Chip Conference (SOCC). Ed. IEEE. Santa Clara, CA: IEEE.
Full Patent
Ganguly, Amlan, et al. "LOOK-UP TABLE CONTAINING PROCESSOR-IN-MEMORY CLUSTER FOR DATA-INTENSIVE APPLICATIONS." U.S. Patent US11775312. 3 Oct. 2023.
Indovina, Mark Allen, et al. "Appliance Network Connectivity Apparatus." U.S. Patent US11196650. 7 Dec. 2021.
Indovina, Mark Allen, et al. "Self-organized Multiple Appliance Network Connectivity Apparatus." U.S. Patent 10,462,022. 29 Oct. 2019.
Published Conference Proceedings
Das, Prangon, et al. "Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware." Proceedings of the 2022 IEEE 35th International System-on-Chip Conference (SOCC). Ed. IEEE. Belfast, United Kingdom: IEEE, 2022. Web.
Gillela, Rohini J., et al. "The IANET Hardware Accelerator for Audio and Visual Data Classification." Proceedings of the 2020 IEEE 33rd International System-on-Chip Conference (SOCC). Ed. IEEE. Las Vegas, NV: IEEE, 2021. Web.
Connolly, Mark, et al. "Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-Memory." Proceedings of the 2021 IEEE 39th International Conference on Computer Design (ICCD). Ed. IEEE. Storrs, CT: IEEE, 2021. Web.
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Journal Paper
Sutradhar, Purab Ranjan, et al. "Look-up-Table Based Processing-in-Memory Architecture With Programmable Precision-Scaling for Deep Learning Applications." IEEE Transactions on Parallel and Distributed Systems 33. 2 (2022): 263-275. Print.
Sutradhar, Purab Ranjan, et al. "pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning." IEEE Computer Architecture Letters 19. 2 (2020): 118 - 121. Print.
Ganguly, Amlan, et al. "The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems." Journal of Low Power Electronics and Applications 8. 1 (2018): 1-36. Web.

Currently Teaching

EEEE-120
3 Credits
This course introduces the student to the basic components and methodologies used in digital systems design. It is usually the student's first exposure to engineering design. The laboratory component consists of small design, implement, and debug projects. The complexity of these projects increases steadily throughout the term, starting with circuits of a few gates, until small systems containing several tens of gates and memory elements. Topics include: Boolean algebra, synthesis and analysis of combinational logic circuits, arithmetic circuits, memory elements, synthesis and analysis of sequential logic circuits, finite state machines, and data transfers.
EEEE-499
0 Credits
One semester of paid work experience in electrical engineering.
EEEE-520
3 Credits
The purpose of this course is to expose students to complete, custom design of a CMOS digital system. It emphasizes equally analytical and CAD based design methodologies, starting at the highest level of abstraction (RTL, front-end)), and down to the physical implementation level (back-end). In the lab students learn how to capture a design using both schematic and hardware description languages, how to synthesize a design, and how to custom layout a design. Testing, debugging, and verification strategies are formally introduced in the lecture, and practically applied in the lab projects.
EEEE-620
3 Credits
The purpose of this course is to expose students to complete, custom design of a CMOS digital system. It emphasizes equally analytical and CAD based design methodologies, starting at the highest level of abstraction (RTL, front-end)), and down to the physical implementation level (back-end). In the lab students learn how to capture a design using both schematic and hardware description languages, how to synthesize a design, and how to custom layout a design. Testing, debugging, and verification strategies are formally introduced in the lecture, and practically applied in the lab projects. Students are further required to choose a research topic in the area of digital systems, perform bibliographic research, and write a research paper following a prescribed format.
EEEE-720
3 Credits
In this course the student is introduced to a multitude of advanced topics in digital systems design. It is expected that the student is already familiar with the design of synchronous digital systems. The lecture introduces the operation and design principles of asynchronous digital systems, synchronous and asynchronous, pipelined and wave pipelined digital systems. Alternative digital processing paradigms are then presented: data flow, systolic arrays, networks-on-chip, cellular automata, neural networks, and fuzzy logic. Finally, digital computer arithmetic algorithms and their hardware implementation are covered. The projects reinforce the lectures material by offering a hands-on development and system level simulation experience.
EEEE-722
3 Credits
Due to continually rising system complexity, verification has become the critical inflection point for complex digital system success or failure. In this course students will study various concepts and technologies related to complex digital system verification with an emphasis on functional verification, top down design flows and advanced methodologies. The class projects reinforce the lectures material by offering hands-on development of a verification environment for a complex digital system.